DDR Memory Controller Design Engineer

Intel
San Jose, CA 95113
  • Job Code
    JR0175914
Job Description

Come join Intel's FPGA Business Unit (Programmable Solutions Group) as a senior level Memory Controller Design Engineer. You will be responsible for researching, designing, developing, and testing Intel's next generation Memory solutions.

As a DDR Memory Controller Designer, you will be involved with all phases of the design of real time, low-latency, high-bandwidth and high-performance DDR (DDR5/LP5) memory solutions. You will work with the memory architecture and drive micro-architecture definition into RTL and final GDS. You will participate in early product definition of next-gen high performance memory controller, micro-architecture development, define testing, physical integration and verification strategy, identify timing bottlenecks and work closely with CAD and PD teams to address it. You will champion development of the best-in-class designs maximizing the Performance/Watt.

Responsibilities:

  • Translate micro-architecture definition into RTL design, drive verification, and documentation of High-performance Memory Subsystem Designs.

  • Determine best micro-architecture, logic design, system validation, training (firmware) and characterization requirements. Including DFT, DFX, Power intent, Signal Integrity and functional coverage analysis.

  • Develop memory hierarchies for high performance and low latency parallel computer architectures.

  • Define module interfaces/formats for physical integration and functional validation. Work closely with peers in layout, structured design, validation, emulation, FPGA software and product characterization groups.

  • Work with Architects and micro-architect (lead) and drive system analysis of total memory system, characterizing performance, QoS, benchmarking studies and publish results.

  • Automate design tasks to complete the design in the most efficient approach. Champion productivity improvement metrics within the hardware organization.

  • Work with all aspects of the SoC design flow from high-level design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing.

  • Analyzes equipment to establish operation infrastructure, conducts experimental tests, and evaluates results. May also review vendor capability to support development.

  • Youll be a self-motivator with a penchant for solving problems at the cutting edge of technology

  • Youll demonstrate strong leadership skills and mentor junior designers.

  • Youll possess excellent interpersonal and communication skills


Qualifications

You must possess the below minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Education

Bachelors Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Minimum Qualifications

10+ years of experience of which should include:

  • SoC design (e.g. digital logic design)

  • Memory experience (e.g. memory system, memory controller, DDR4/5, LPDDR4/5, etc.)

Preferred Qualifications

  • 15+ years of frontend design/digital logic experience

  • Experience in high performance memory subsystem, including DRAM controller, AXI interface, DFI interface and DRAM interface calibration/training mechanisms and algorithms

  • Experience in DDR5, LPDDR5, NVDIMM, ONFI, 3D-Xpoint memory, Memory Encryption, Coherency, Caching and NOC architectures

  • MS or PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field

Inside this Business Group

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.



Other Locations

US, California, Folsom;US, California, Santa Clara;US, Oregon, Hillsboro;US, Oregon, Portland;US, Texas, Austin



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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DDR Memory Controller Design Engineer

Intel
San Jose, CA 95113

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