DDR IO Architect

Intel
San Jose, CA 95113
  • Job Code
    JR0199159
  • Jobs Rated
    187th
Job Description

Come Join Intel's Ethernet Products Group (EPG) within the Intel's Data Platforms Group (DPG). DPG drives new product technologies, from high-end coprocessors for supercomputers to low energy systems for enterprise and the cloud, as well as solutions for big data and intelligent devices. The EPG SiE is responsible on all Smart  Ethernet network cards and Technologies team is seeking experienced Network Software Engineers to join an established team working on defining the next gen DDR subsystem. This is an exciting pre-silicon and post-silicon role defined and support the memory subsystem tools, and topologies, deep involvement in all select IPs and design process.

 

The Candidate will be part of IO technology team, responsible for future DDR subsystem (controller and PHY) and support existing DDR Memory Interfaces.

 

In this role, your daily agenda will be anything but ordinary. On a regular basis, it will include but not limited to:

  • Defining, Documenting and Designing Architectures for Memory Interfaces supporting multiple topologies and configuration
  • Owning sub system parameters. Determine, specify and evaluate complex hardware features and structures and ensure that firmware and hardware designs interface according to requirement
  • Defining, documenting, and testing processes for inclusion into technical platforms, subsystem specifications, input/output and working parameters for hardware and/or firmware compatibility
  • Deep involvement in Modeling, Architecture meeting latest Memory Industry Standards for LPDDR/X, DDR
  • Identifying, analyzing and resolving subsystem design weaknesses
  • Owning Memory selection level architecture study and recommending system-level design trade-off aligned to IP/SoC requirement and roadmap
  • Collaborating across functional teams - Logic, Circuit, Verification, Structural Design in PHY level definition meeting Best In Class Power, Performance and Area metrics
  • Collaborating with SoC integration teams on PHY level requirement and integration issues

Additional soft skills needed for this role include:

  • Strong written communication and presentation skills


Qualifications

Candidates must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Requirements listed below would be obtained through a combination of Industry job relevant experience, internship experiences and or schoolwork/classes/research.

Minimum Education:

  • Bachelor of Science degree in Computer Science, Computer Engineering, Electrical Engineering or similar field of study

Minimum Qualifications:

  • 5+ years of experience in PHY Architecture, Circuit/Logic Micro-Architecture definition of High Speed Memory Interfaces (example DDR, LPDDR, GDDR, Die-to-Die IO, PCIe, Serdes.)
  • 10+ years of hands-on experience in high speed design building blocks for High Speed Interfaces, RTL logic design, Synthesis, Physical design, Power analysis and/or integration aspects for IO PHY in SoC
  • 3+ years of LPDDR/DDR/GDDR JEDEC specifications and related Memory Interface Protocols
  • 10+ years of experience in any of the following Cross-disciplines (Analog integration, RTL/System Verilog, Static timing analysis concepts, APR, Floor-planning, Metal-routing, Power-grid, Memory IO training and Architecture specification documentation.)

Preferred Qualifications:

  • Master of Science degree

Inside this Business Group

The Data Center Group (DCG) is at the heart of Intels transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologiesspanning software, processors, storage, I/O, and networking solutionsthat fuel cloud, communications, enterprise, and government data centers around the world.


Intel Corporation will require all new U.S. employees to be fully-vaccinated for Covid-19 as a condition of hire unless they have an approved accommodation in place under applicable law. Newly-hired employees will be required to provide proof of vaccination prior to their start date.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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DDR IO Architect

Intel
San Jose, CA 95113

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Architect
187th2019 - Architect
Overall Rating: 187/199
Median Salary: $79,380

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190/220
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183/220