CPU Backend Engineer for Full-Chip Timing

Austin, TX 78701
  • Job Code
Job Description
Become a key member of a team participating in the Integration and Verification of a future Intel CPU!

This position requires an Engineer with broad Physical Design and STA skills, coupled with leadership skills necessary to drive methodology and to collaborate effectively with multiple functional teams within the CPU design team. We are looking for a highly motivated and technically savvy experienced Engineer to drive the timing convergence for Full-Chip (FC) models.

As a FC Design Engineer, you will perform constraints management and STA verification. You will also be responsible for coordinating collateral handoffs between the FC Design team and other functions within back-end design such as Clocking, Power Delivery and Partition synthesis/APR. You will drive timing closure and provide collateral for SOC drops.

In addition to the qualifications listed below, the ideal candidate will also exhibit behavioral traits that indicate:

  • Teamwork and collaboration skills in a high-paced atmosphere
  • Productive under demanding schedules
  • Excellent written and verbal communications skills
  • Self-motivator with strong problem solving skills


You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork/classes/research and/or relevant previous job and/or internship experiences. This is an entry level position and will be compensated accordingly.

Minimum Qualifications:

The candidate must have a Bachelor's in Electrical/Computer Engineering and 1+ years of experience OR a Master's degree in Electrical/Computer Engineering and experience in:

  • Back-end design and/or integration
  • Static Timing Analysis including constraint generation, clock stamping and timing closure
  • Perl and Tcl scripting

Inside this Business Group

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intels products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moores Law and groundbreaking innovations.  DEG is Intels engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Other Locations

US, Oregon, Hillsboro

Intel Corporation will require all new U.S. employees to be fully-vaccinated for Covid-19 as a condition of hire unless they have an approved accommodation in place under applicable law. Newly-hired employees will be required to provide proof of vaccination prior to their start date.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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CPU Backend Engineer for Full-Chip Timing

Austin, TX 78701

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