CPU Backend Engineer for Full-Chip Timing

Intel
Austin, TX 78701
  • Job Code
    JR0162988
Job Description

Become a key member of a team participating in the Integration and Verification of a future Intel CPU. This position requires an Engineer with broad Physical Design and STA skills coupled with leadership skills necessary to drive methodology and to collaborate effectively with multiple functional teams within the CPU design team.

We are looking for a highly motivated and technically savvy experienced engineer to drive the physical and timing convergence of a FullChip FC assembly of partitions. As a FC Design Engineer you will perform constraints management and STA verification .

You will also be responsible for coordinating collateral handoffs between the FC Design team and other functions within backend design such as Clocking Power Delivery and Partition synthesis APR and will drive timing closure and provide collateral for SOC drops.

In addition to the qualifications listed below the ideal candidate will also exhibit behavioral traits that indicate

  • Teamwork and collaborative in a high paced atmosphere

  • Productive under demanding schedules

  • Excellent written and verbal communications skills

  • Strong leadership skills with the willingness to mentor junior designers

  • Self motivator with strong problem solving skills


Qualifications

You must possess the below minimum qualifications to be initially considered for this position Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates

Minimum Qualifications

Candidate must have a Bachelors degree in Electrical Computer Engineering and 8 years of experience in with OR a Masters degree in Electrical Computer Engineering and 6 years of experience in with

  • Backend design andor integration

  • Static Timing Analysis including constraint generation clock stamping and timing closure

  • Synthesis APR flows on multi voltage high frequency designs

  • Multiple Power Domain Analysis using UPF

  • Noise crosstalk OCV analysis

  • Tcl scripting


Preferred Qualifications

  • 5 years experience in with Fusion Compiler DCT DCE ICC2 RedHawk ICV Conformal Calibre PrimeTime Star RCXT

  • Full chip integration experience

Inside this Business Group

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intels products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moores Law and groundbreaking innovations.  DEG is Intels engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.



Other Locations

US, Oregon, Hillsboro


Intel Corporation will require all new U.S. employees to be fully-vaccinated for Covid-19 as a condition of hire unless they have an approved accommodation in place under applicable law. Newly-hired employees will be required to provide proof of vaccination prior to their start date.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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CPU Backend Engineer for Full-Chip Timing

Intel
Austin, TX 78701

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