Component Design Engineer

Folsom, CA 95630
  • Job Code
Job Description

The Production Libraries Group is looking for an experienced standard cell library design engineer in the area of standard cell library design and validation using Intel latest process technology for use by Intel CPU, Atom, Graphics, mixed signal IPs, Client, Sever, Chipset projects and IFS Foundry customers.

The successful candidate will be part of the Production Libraries team responsible for standard cells validation enablement doing ASIC Design Flow execution, validation automation development and maintenance, and design issues resolution.

Responsibilities include, but are not limited to:

  • Perform ASIC design flow enablement, execution, PPA (Power, Performance, Area) analysis, synthesis, APR, and layout verification
  • Publish library PPA and trend analysis reports
  • Design and develop automation to ensure high quality of standard cell library models utilizing a combination of internal and industry design tools
  • Debug, root cause, and drive alignment and improvements in standard cell modeling
  • Develop regression automation to identify tool compliance issues quickly and work with vendors for solutions

Traits we're looking for in a candidate:

  • Possesses excellent written and verbal communication skills
  • Strong customer/result orientation and the ability to work with external, internal partners and with EDA vendors in a flexible manner


You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

Candidate must have a Bachelor's degree in the field of electronics engineering or hardware engineering, Electrical and/or Computer Science/Engineering or related fields with 3+ years of experience -OR- a Master's degree in the field of electronics engineering or hardware engineering, Electrical and/or Computer Science/Engineering or related fields with 2+ years of experience in/with:

  • ASIC Design - PPA(Power Performance Area) Analysis, Block Setup, Design Flow Enablement, Synthesis/APR, Timing, Layout Verification
  • Proficiency with Industry standard ASIC tools Fusion Compiler, ICC2, Primetime, Innovus
  • Scripting/programming languages such as Tcl or Python or Perl or Linux
  •  Automation experience in one or more areas of VLSI Design Automation (Physical Design Automation or Simulation or Timing Analysis or Reliability Analysis)

Preferred Qualifications:

  • Proficiency with Industry standard ASIC tools - Design Compiler, Genus, Tempus, ICV 
  • Experience in digital circuit design, front end model creation and functional verification.
  • Digital circuit design, including CMOS combinatorial logic and sequential element design and layout. Good understanding of device physics.
  • Extensive experience with standard cell library characterization, liberty models and cross validations with front end models and liberty models.
  • Extensive experience working with EDA vendors to drive new features and capabilities.
  • Knowledge of industry-standard EDA tools for VLSI circuit and layout design.
  • Experience working in the Linux environment and its development tools.
  • Standard cell level PPA modeling, simulation, and ROI analysis.
  • Experience in CMOS power modeling and cell level optimization.
  • CMOS and standard cell level device variation and Aging analysis.
  • Engineering acumen and analytical skills.
  • Debugging skills.
  • Customer oriented and able to work in a dynamic environment.
  • Experience leading and mentoring junior engineers.

Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

Other Locations

US, California, Santa Clara;US, Oregon, Hillsboro

Intel Corporation will require all new U.S. employees to be fully-vaccinated for Covid-19 as a condition of hire unless they have an approved accommodation in place under applicable law. Newly-hired employees will be required to provide proof of vaccination prior to their start date.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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Component Design Engineer

Folsom, CA 95630

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