Compiler Engineer

Intel
Santa Clara, CA 95050
  • Job Code
    JR0177385
Job Description

Come and join Intel as we are seeking highly qualified candidates to join our Data Platform Group (DPG) as a Compiler Engineer. We are Barefoot Networks Switching Division (BXD) in Intel's DPG and we're a team of visionaries, experienced technologists, and engineers with a proven track record of success who have created a blueprint for designing and operating the world's fastest and most programmable networks. Our team is driven by deep engineering skills and a love of cutting-edge projects. We are building the world's fastest switches that are also fully programmable, ensuring the network can adapt to meet the emerging needs of applications and empower users to write solutions rapidly and to innovate broadly. We believe that with full programmability the networking industry will enjoy the same explosion of innovation as we have seen in computing - cloud and mobile.

Programmable data planes enable a whole new ecosystem of advanced networking applications, and the field of possibility is mind-bogglingly wide. It ranges from advanced network monitoring, analysis, and diagnostics, to building a large-scale data analysis platform, to embedding some middle-box functions in switches/routers, and to jointly designing a network and the apps running on the network. At the core of this revolution are the technologies that we are building languages, compilers, and tools co-designed with fully programmable hardware. We're just starting to scratch the surface of this novel and exciting area, and we're looking for passionate engineers who can join this amazing journey with us. In this position you will gain invaluable experience which will allow growth and expanded opportunities within this business group as well as future possible opportunities with other business groups within Intel.

In this role you will be responsible for compiling and tool development for domain-specific languages and architectures for high-performance programmable networks.

Additional responsibilities will include, but are not limited to:

  • Contribute to the technical development of the compiler suite designed for P4, a new domain-specific language and targets the novel architecture of the fastest networking chip (Tofino)

  • Responsible for the definition, design, development, test, debugging, release, enhancement, and maintenance of software tools for the P4 domain specific language

  • Responsible for both proprietary and open source software development for compilers and tools for programmable network architectures

  • Contribute to the P4 language design and standardization and enable it to capture the semantics of new networking applications, allowing you to design new compiler optimizations specifically targeted for networking applications

  • Design and develop tools that enable the P4 ecosystem and networking applications

  • Work with hardware teams to define compilation and optimization algorithms supported by hardware features for the networking domain

  • Provide code reviews to peers


The ideal candidate will have the following skills in addition to the qualifications listed below:

  • Team player, with a demonstrated experience to technically influence others

  • Strong problem-solving skills

  • Excellent verbal and written communication skills


Qualifications

Qualifications You must possess the below minimum qualifications to be initially considered for this position Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Required Qualifications:

Candidate must have Bachelors or Master's degree in Electrical Engineering, Computer Science or related field.

4+ years of industry experience as Bachelors or 3+ years of industry experience as Masters in the following areas:

  • C/C++ programming

  • System software architecture design implementation

  • Debugging and understanding complex software systems

Preferred Qualifications:

  • PhD is preferred

  • Optimizing compiler backends register allocation code scheduling

  • Code versioning systems github

  • Contributing to open source projects

  • Networking applications

  • Program synthesis and verification

  • Domain specific language design and implementation

  • Hardware modeling and simulation tools

  • Constraint satisfaction problem solving techniques

  • Continuous integration frameworks Jenkins Travis

Inside this Business Group

The Data Center Group (DCG) is at the heart of Intels transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologiesspanning software, processors, storage, I/O, and networking solutionsthat fuel cloud, communications, enterprise, and government data centers around the world.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Before you go...

Our free job seeker tools include alerts for new jobs, saving your favorites, optimized job matching, and more! Just enter your email below.

Share this job:

Compiler Engineer

Intel
Santa Clara, CA 95050

Join us to start saving your Favorite Jobs!

Sign In Create Account