Clocking Design Engineer

Intel
Austin, TX 78701
  • Job Code
    JR0188110
Job Description

In this role responsibilities include, although not limited to:

  • Oversees definition, design, verification, and documentation for SoC (System on a Chip) development
  • Determines architecture design, logic design, and system simulation
  • Defines module interfaces/formats for simulation
  • Performs Logic design for integration of cell libraries, functional units and subsystems into SoC full chip designs, Register Transfer Level coding, and simulation for SoCs
  • Contributes to the development of multidimensional designs involving the layout of complex integrated circuits
  • Performs all aspects of the SoC design flow from highlevel design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing
  • Analyzes equipment to establish operation infrastructure, conducts experimental tests, and evaluates results
  • May also review vendor capability to support development

The ideal candidate should exhibit behavior traits that indicate:

  • Willing to work well in a team and be productive under aggressive schedules
  • Creative problem solving skills
  • Self-motivated and well organized
  • Strong written and verbal communications skills to interface with other teams


Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork/classes/research and/or relevant previous job and/or internship experiences. This is an entry level position and will be compensated accordingly.

Minimum Qualifications:


You must possess a Masters in Electrical Engineering or Computer Engineering or equivalent.

Preferred Qualifications:

Experience in:

  • Perl and TCL coding
  • Synthesis, APR and timing tools and flows
  • Circuit design
  • Lower power design
  • Device physics
  • Clock network design and clock tree synthesis

Inside this Business Group

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intels products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moores Law and groundbreaking innovations.  DEG is Intels engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.



Other Locations

Virtual US and Canada


Intel Corporation will require all new U.S. employees to be fully-vaccinated for Covid-19 as a condition of hire unless they have an approved accommodation in place under applicable law. Newly-hired employees will be required to provide proof of vaccination prior to their start date.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Annual Salary Range for jobs which could be performed in US, Colorado:
$82,210.00-$123,570.00


Benefits:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, and benefit programs. Find more information about our Amazing Benefits here
Intel is committed to a culture of accessibility.  Intel provides accommodations to applicants and employees with disabilities.  Find information and request accommodation here

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Clocking Design Engineer

Intel
Austin, TX 78701

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