Circuit Edit - Research Engineer

Intel
Santa Clara, CA 95050
  • Job Code
    JR0180439
Job Description

Intel is seeking highly qualified candidates to join our silicon debug technology development team as a Circuit Edit technology research-engineer. As a circuit edit R&D engineer, you will be responsible for performing characterization and development for new generations of focused ion beam (FIB) platforms and ion beam technologies (e.g., Xenon Plasma FIB; Gallium FIB; Neon/Helium FIB; cold beams, etc.). This includes developing design of experiments, executing DOEs, performing integrated circuit testing, and performing various types of analysis (SEM, EDS, cross section, etc.). Responsibilities include developing complex ion beam machining strategies to enable modification of integrated circuits on industries most advance process technology nodes such as power-gate and Ribbon-FET technologies. Candidate should have a passion for hands-on tool & lab operations work, performing debug and testing on the latest cutting edge debug equipment and technologies. 

Additional responsibilities include collaborating with the operation support team, circuit designers, component debug engineers, platform validation engineers, yield FA/FI engineers, and process technology developers to collaborate on identifying capability opportunities and developing best practices for ion beam machining for debug / defect analysis.  Candidate should have strong written and verbal skills, willing to create training and documentation, and be willing to work both independently and collaboratively with teams across multiple organization and geographies.


Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Education:

Candidate must possess a Bachelors degree in Electrical Engineering, Computer Engineering, Chemical Engineering, Material Sciences or a related field with 4+ years experience -OR- a Masters degree in Electrical Engineering, Computer Engineering, Chemical Engineering, Material Sciences or a related field with 3+ years experience -OR- a PhD in Electrical Engineering, Computer Engineering, Chemical Engineering, Material Sciences or a related field with 1+ years in the following:

Minimum Qualifications:

  • Background in circuit layout, and/or process technology
  • Hands on experience in vacuum technology and electron and/or ion microscopy

Preferred Qualifications:

  • Additional hands on TEM, EDS, SIMS, pico-probe station, and light optical microscope experience
  • Experience-understanding of: ion / electron optics; plasma etch or beam induced chemistry material reaction; ion implant / ion-solid interaction modeling
  • Background in device physics
  • Strong interest in hands on application development work

Inside this Business Group

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intels products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moores Law and groundbreaking innovations.  DEG is Intels engineering group, supplying silicon to business units as well as other engineering teams.  As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.


Intel Corporation will require all new U.S. employees to be fully-vaccinated for Covid-19 as a condition of hire unless they have an approved accommodation in place under applicable law. Newly-hired employees will be required to provide proof of vaccination prior to their start date.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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Circuit Edit - Research Engineer

Intel
Santa Clara, CA 95050

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