CAD Engineer - STA Signoff Lead

Cupertino, CA 95014
  • Job Code
    200172385
Summary

Summary

Posted: Jun 18, 2020

Role Number:200172385

Do you love building elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As p...Summary

Summary

Posted: Jun 18, 2020

Role Number:200172385

Do you love building elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions! Joining this group means you'll be responsible for crafting and building the technology that fuels Apple's devices. Together, you and your team will enable our customers to do all the things they love with their devices.

A Signoff Engineer ensures that all critical and appropriate verification and analysis work has been performed on a design before tapeout. In this high-visibility position you will own the definition, development, and implementation of signoff requirements for STA, Noise, and Clocks of high-volume state-of-the-art SOC, working with other teams in the organization to verify that the EDA flows and tools are set up and run correctly during the project, and all signoff criteria are met at the end of the project. This role also requires direct interaction with technology, CAD, and design groups to provide frontline support for enablement, enhancement, and debug requests.

Key Qualifications

  • The ideal candidate will have:
  • Deep knowledge of STA and Noise analysis flows and tools
  • Experience in timing closure, clock tree construction, and signal integrity
  • Spice simulation for path analysis and tools correlation
  • Solid understanding of PNR Analysis tools such as Primetime and Tempus
  • Proficiency with programming using Perl and Tcl
  • Ability to work in a fast paced, collaborative environment

Description

As the CAD STA Signoff Lead, you will:
- Determine signoff criteria for STA, Signal Integrity, and Clock construction / simulation
- Work with Integration, DFT, CAD, Tech, Power, and PNR teams
- Participate in technology and design reviews for options of assessing critical timing interfaces
- Develop and maintain signoff checks and scripts for signoff verification
- Resolve signoff timing requirements across all modes and corners
- Verification of CAD flows
- Drive signoff reviews with design teams
- Enable design teams for signoff
- Milestone and signoff scheduling. Signature delegation and tracking

Education & Experience

BS/MS in EE/CS/CE or equivalent.

Additional Requirements

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CAD Engineer - STA Signoff Lead

Apple, Inc.
Cupertino, CA 95014

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