ASIC/FPGA Logic Designer

Folsom, CA 95630
  • Job Code
Job Description

If you are a strong ASIC/FPGA design engineer with a passion for logic design and working on Intel's latest SoC architecture then our Intel Validation Engineering (IVE) department has an opportunity for you. IVE is responsible for silicon validation of nearly every SoC product across both server and client segments. Content and Coverage Solutions (CCS) in IVE delivers leading edge solutions for validation of server and client SoCs. You'll be joining a strong team with a clear vision of delivering Intel's validation tool solutions by using creativity and innovation. Logic design engineer for cutting-edge high-speed protocols: PCIe, CXL, USB. Performs logic design, Register Transfer Level (RTL) coding, and simulation to generate cell libraries, functional units and subsystems for inclusion in full chip designs. Participates in the development of architecture and microarchitecture specifications for the logic components. Provides IP integration support to SoC customers and represents RTL team.

The ideal candidate WILL exhibit the following behavioral traits:

  • Self-motivated individual willing to take and follow directions and deliver to schedule
  • Quantitative, analytical, and problem-solving skills, problem/conflict resolution skills
  • Ability to work independently and at various levels of abstraction
  • Strong analytical ability, problem solving and communication skills


You must possess the below minimum qualifications to be initially considered for this position Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.  Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates

Minimum Qualifications:

Must have a BS and 4+ years of experience OR MS in Electrical Engineering, Computer Engineering, Computer Science or related, and 3+ years of experience

  • Experience in RTL/Logic design on ASICs or FPGA IP blocks or SOCs using System Verilog RTL coding
  • Experience writing micro architectural specifications.
  • Experience developing and debugging complex logic design
  • Experience interfacing with pre-Si verification and physical design teams

Preferred Skills:

  • Experience with PCIe and/or CXL
  • Familiarity with a range of internal and 3rd-party logic design tools
  • Gate-level understanding of RTL and synthesis - i.e. understand how RTL looks like/behaves after it is synthesized into gates
  • Experience using lab equipment such as logic analyzers, scopes, protocol analyzers and the ability to use them to debug issues

Inside this Business Group

The everyday contributions of the Intel Validation Engineering (iVE) team are essential to retaining/regaining Intel's product leadership. We validate, debug, and tune the newest designs and world-changing technologies that enrich the lives of every person on earth. We play a critical role in completing the PRQs of Intel products and in Intel's ability to deliver the annual technology platforms in our roadmap.

Other Locations

US, California, Santa Clara;US, Oregon, Hillsboro;US, Texas, Austin

Intel Corporation will require all new U.S. employees to be fully-vaccinated for Covid-19 as a condition of hire unless they have an approved accommodation in place under applicable law. Newly-hired employees will be required to provide proof of vaccination prior to their start date.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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ASIC/FPGA Logic Designer

Folsom, CA 95630

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