Analog Mixed-Signal Modeling Verification Engineer

Cupertino, CA
  • Job Code
    200106769
Summary

Summary

Posted: Sep 26, 2019

Weekly Hours: 40

Role Number: 200106769

Would you like to join Apple's growing cellular wireless design team? Do you thrive on pushing the simulation and modeling limits of highly complex RF cellular transceivers in advanced technology nodes? Our team is responsible for all aspects of cellular silicon development with a particular emphasis on highly integrated and efficient designs and technologies that transform the user experience at the product level

As an analog mixed-signal (AMS) verification engineer, you will get to work on modeling analog building blocks used in PLLs, ADCs, DACs, RF receiver and transmitter, and define test plans with the design team to validate the full functionality of the transceivers with all digital controls and calibrations to guarantee successful Silicon bring up without functional bugs. By joining us, your creativity and drive for continuous improvement will help us build strong methodologies and design products with high level of quality that will continuously outperform previous generations and improve the product experience for our customers across the world

In this role, you will be verifying RF/Analog/Mixed-Signal blocks and SOCs using SystemVerilog to create testbenches, checkers, models and tests. You will build and execute test plans to meet project schedule and metric requirements, including coverage metrics

Key Qualifications

  • We want you to have 5+ years of industry verification experience with RF/Mixed-Signal blocks and SOCs
  • Expertise building Mixed-Signal test benches, checkers and tests
  • Solid experience with creating and using real-numbered analog behavioral models in SystemVerilog or other language
  • Experience in HVL and HDL (SystemVerilog, Verilog)
  • Strong verification skills in problem solving, constrained random testing, and debugging
  • Good understanding of common analog/RF blocks
  • Experience with HVL methodology (UVM/OVM/VMM) a plus
  • Experience with signal processing using Python or Matlab a plus
  • Experience with Virtuoso Composer, ADE and HED a plus
  • Team spirit, excellent communication skills and the desire to take on diverse challenges are essential to have

Description
- Review specifications, extract features, define and execute verification plan
- Develop top/block level Mixed Signal and Digital testbench, and generate directed/ constrained random tests in a UVM framework
- Build and reuse real numbered analog behavioral models, monitors, and checkers for RF/Mixed-Signal blocks
- Debug failures, fix testbench/model/checker issues, manage bug tracking, and analyze and close coverage
- Write scripts for automation of flow
- Improve Mixed Signal verification methodology

Education & Experience

MSEE is required; PhD would be an advantage

Additional Requirements

  • Apple is an equal opportunity employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants


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Analog Mixed-Signal Modeling Verification Engineer

Apple, Inc.
Cupertino, CA

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