Analog/Mixed Signal Design Engineer

Intel
San Jose, CA 95113
  • Job Code
    JR0183044
Job Description

As an Analog/Mixed Signal Design Engineer your responsibilities will include but not limited to the following:

  • Innovate and design of mixed-signal circuits such as high speed TX, RX, equalization circuitry, DLL, clock distribution, high voltage IO, level shifter, on-die VREG/LDO, RCOMP/SCOMP and VREF blocks to meet architectural specifications.
  • Design and deliver circuit building block schematic, perform pre layout and post layout design optimization to meet design specification across PVT, process variation sensitivity analysis, aging, EOS, RV checks for design reliability.
  • Own design verification plans covering functionality, performance and reliability meeting high volume productization requirement.
  • Collateral generations like circuit Integration spec, UPF, PERC, BMOD, timing model, power model, ICCT, IBIS, alpha numbers.
  • Collaborate with custom layout engineer, logic designer, logic verification designer, structural physical design engineers, signal integrity and power deliver engineer to define clear collateral handoff requirements to ensure efficient IP integration.
  • Perform post silicon data analysis and debug and make necessary design enhancement to meet design specification.

 

In addition the ideal candidate should exhibit the following behavioral traits:

  • Good communication and presentation skills to enable cross functional collaboration.
  • Effective prioritization and time management skills.
  • Willing to work in a dynamically changing environment, which requires ingenuity and skills to solve issues.
  • Be a team player and pro-active problem solver, willing to work autonomously and also collaboratively in a team environment.


Qualifications

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Education Requirements

  • Bachelors Degree in Electrical Engineering or equivalent with a minimum of 5 years of experience in analog/mixed sign, high speed, or high voltage IO designs or Masters Degree in Electrical Engineering or equivalent with a minimum of 3 years of experience in analog/mixed sign, high speed, or high voltage IO designs or a PhD in Electrical Engineering or equivalent with a minimum of 1 years of experience in analog/mixed sign, high speed, or high voltage IO designs.

Minimum Qualifications

  • 3 years of experience with direct design experience with analog and mixed signal circuits like amplifiers, comparators, regulators, etc.
  • 3 years of experience with analog/mixed signal circuit design and layout flow and running post-layout simulations.

               

Preferred Qualifications

  • Experience in Verilog PNR and static timing analysis.
  • Experience in IP and Sub-system Architecture.

Inside this Business Group

The Programmable Solutions Group (PSG) was formed from the acquisition of Altera. As part of Intel, PSG will create market-leading programmable logic devices that deliver a wider range of capabilities than customers experience today. Combining Altera's industry-leading FPGA technology and customer support with Intel's world-class semiconductor manufacturing capabilities will enable customers to create the next generation of electronic systems with unmatched performance and power efficiency. PSG takes pride in creating an energetic and dynamic work environment that is driven by ingenuity and innovation. We believe the growth and success of our group is directly linked to the growth and satisfaction of our employees. That is why PSG is committed to a work environment that is flexible and collaborative, and allows our employees to reach their full potential.



Other Locations

US, Oregon, Hillsboro;US, Texas, Austin



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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Analog/Mixed Signal Design Engineer

Intel
San Jose, CA 95113

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