Analog Engineer

Folsom, CA 95630
  • Job Code
Job Description

Our High Speed IO group within IP Engineering Group (IPG) is looking for an Analog Design Engineer to play a critical role in the high-speed IO designs of next generation PHYs. You will be part of a high-speed IO IP design team responsible for delivering state of art low power high performance IO IP design on multiple process nodes for DDR/PCIE/Type-C PHYs.The Analog Circuit Design Engineer designs, develops, modifies and evaluates complex analog and mixed signal electronic parts, components or integrated circuitry for analog and mixed signal electronic equipment and other hardware systems. This role is responsible for the design and development of electronic components. Additional Responsibilities may include (but are not limited to): Design of analog mixed signal IP and chip layout Conduct circuit simulations and checking Complete device evaluation and characterization, Document specifications Complete prototype construction and checkout Modify and evaluate semiconductor devices and components Perform developmental and/or test work Review product requirements and logic diagrams Plan, organize, and design projects or phases of design projects. Respond to customer/client requests or events as they occur. Develop solutions to problems utilizing formal education and judgement.


Job Qualifications:

Candidate must possess a Masters degree in Electrical Engineering, Computer Engineering or other related field of study with 3+ years experience -OR- a PhD degree in Electrical Engineering, Computer Engineering or other related field of study with experience in the following:

Minimum Qualifications:

- Knowledge of SOC/IP high speed IO analog/mixed signal circuit design including: designing, testing and validating analog and/or mixed signal circuits with sub-micron CMOS technology.
- Knowledge of analog layout techniques, including floor-planning, matching, shielding and parasitic optimization
- Strong background in VLSI and industry standard CAD tools for schematic capture, simulation, layout and physical verification (examples: Cadence adexl, Spectre/Ultrasim/AMS Designer /Virtuoso)

Preferred Qualifications:

- Some experience in high speed IO circuit design in any of these areas: Rx, Tx, LDO, PLL, DLL, and clocking circuits
- Solid understanding of deep sub-micron device physics, process technology and manufacturing

Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

Other Locations

US, California, Santa Clara

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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Analog Engineer

Folsom, CA 95630

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