Analog Engineer

Intel
Folsom, CA 95630
  • Job Code
    JR0177575
Job Description
Our High Speed IO group within IP Engineering Group (IPG) is looking for an Analog Design Engineer to play a critical role in the high-speed IO designs of next generation PHYs. You will be part of a high-speed IO IP design team responsible for delivering state of art low power high performance IO IP design on multiple process nodes for PCIE/Type-C PHYs. The Analog Circuit Design Engineer designs, develops, modifies and evaluates complex analog and mixed signal electronic parts, components or integrated circuitry for analog and mixed signal electronic equipment and other hardware systems. This role is responsible for the design and development of electronic components. Additional Responsibilities may include (but are not limited to): Design of analog mixed signal IP and chip layout Conduct circuit simulations and checking Complete device evaluation and characterization Conduct timing analysis using silicon smart and primetime STA tools Document specifications Modify and evaluate semiconductor devices and components Perform developmental and/or test workIn addition to the qualifications listed below the ideal candidate will also have: Excellent analytical and problem-solving skills Strong verbal/written communication skills Effective team player with continuous learning mindset Willingness to balance multiple tasks Willingness to work in a fast-paced environment and have as much fun and growth as possible in the process


Qualifications

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum Qualifications: Candidate will have a Master's degree in Electrical Engineering, Computer Engineering, or other related field of study with 2+ years of industry experience OR Bachelor's degree in Electrical Engineering, Computer Engineering, or other related field of study with 4+ years of industry experience in: Designing, testing and validating analog and/or mixed signal circuits with sub-micron CMOS technology. High speed IO circuit design including but not limit to LDO, PLL, DLL, Rx, Tx and clocking circuits. Solid understanding of deep sub-micron device physics, process technology and manufacturing. Knowledge of analog layout techniques, including floor-planning, matching, shielding and parasitic optimization. Strong background in VLSI and industry standard CAD tools for schematic capture, simulation, layout and physical verification, such as Cadence Spectre/Ultrasim/AMS Designer /Virtuoso.Preferred Qualifications: Experience with Timing analysis of analog IPs using silicon smart or primetime

Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.



Other Locations

US, California, Santa Clara



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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Analog Engineer

Intel
Folsom, CA 95630

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