Analog Design Engineer

Intel
Santa Clara, CA 95050
  • Job Code
    JR0180419
Job Description

IPG is looking for an Experienced Analog Design Engineer to contribute towards NextGen Data center Memory IO Design for Intel's High-Performance Data center Microprocessors.

Responsibilities include but not limited to:

  • Technology path finding, specification, and design of complex analog and mixed signal circuits, custom analog layout supervision, documentation, DFT/DFM and post silicon validation.
  • Analog circuit design responsibilities consist of high speed IO (HSIO) transmitters (Tx) and receivers (Rx), amplifiers (Op-Amps), equalizers (CTLE, DFE), filters, high performance low-jitter clocking, on-die voltage regulators (LDO) and references (BGR), signal integrity analysis, system level modeling, power delivery, supply noise sensitivity reduction (Bias generation and distribution), feedback loop analysis, stability, compensation, poles-zeros and other elements necessary to design, verify and productize high performance analog IO solutions.

Additional responsibilities include

  • Mentoring junior designers,
  • Collaborating with other design disciplines, and contributing to design reviews.
  • Ability to work independently with minimal supervision.
  • Be creative, accountable, and quick to make good decisions


Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

The candidate must have a Masters degree in Electrical Engineering or Computer Engineering with 2+ years of experience OR a PhD degree in Electrical Engineering or Computer Engineering in lieu of work experience with:

  • Understanding of VLSI Analog circuit design tradeoffs, small signal analysis, digital design and building blocks (flops, latches, sizing, boolean algebra)
  • Familiarity with design tools and flows such as Synopsys, Cadence



Preferred Qualifications

  • Knowledge of highspeed IO signaling, transmission line theory, power delivery power and signal integrity and power integrity concepts, PLL, Noise analysis, Jitter, clocking, ADC, DAC, Switched-Cap circuits
  • Memory IO training, Firmware, IO link training algorithms, Micro-architecture specification documentation
  • Reliability: RV, ESD, Aging, Electrical overstress
  • Cross discipline knowledge in any of these areas: Analog integration, RTL, System Verilog, Static timing analysis, APR, Floor planning, Metal routing, PowerGrid
  • Software: Matlab, Scripting
  • Post-Si knowledge: Si characterization, Lab equipment (Oscilloscopes, BERT, VNA, signal generators)

Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.



Other Locations

US, Massachusetts, Hudson



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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Analog Design Engineer

Intel
Santa Clara, CA 95050

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