3DIC STCO SOC/Physical Design Engineer

Intel
Hillsboro, OR 97123
  • Job Code
    JR0183445
Job Description

The Design Technology Pathfinding (DTP) organization in Design Enabling (DE) is chartered to identify and drive key strategic initiatives in the pathfinding of technologies for 2023 and beyond, as a holistic Design co-optimization across the Product stack from System architecture to silicon as we extend DTCO to STCO. The job requires partnering and leveraging domain experts across Intel and EDA Eco-System

Your responsibilities may include, but not be limited to:

  • Establish 3DIC Test Cases across market segments
  • Development of 3DIC construction and validation methodology. Evaluation and feedback of 3D-IC TFM and EDA capabilities
  • Test Chips validation of 3DIC technology and methodology
  • Design analysis and feedback for 3D silicon and packaging technologies development
  • Collaboration with the different Product teams to identify critical product characteristics and target setting requirements.
  • Circuit Design analysis and design optimization of 3D advanced silicon/package technology features to enable strong product differentiation

Important behavior traits we look for:

Self-motivated, out of the box thinker with excellent analytical and problem-solving skills


Qualifications

You must possess the below requirements to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork and/or classes and/or research and/or relevant previous job and/or internship experiences.

Minimum Qualifications
MS degree in Electrical or Computer Engineering or a PhD Degree with 1+ years of related experience in the following:

  • VLSI Design
  • IP/Chip Physical design optimization, EDA tools and methodologies for optimal Performance/Power/Area/Cost
  • Scripting skills using a programming language such as Python, TCL


Preferred Qualifications

  • Knowledge of 3D Silicon and 3D packaging technologies
  • Power Management Network Design Methodology (PDN IR/EM, Thermal)
  • Low-power design and clock gating.
  • Reference design and TFM for STCO/3DIC
  • Experience with ARM-based IP PPA optimization
  • Design for Test (DFT) and Design for Debug (DFD)
  • Circuit design and silicon technology. Design challenges in advanced technologies.


#designenablement
#LI-JR1 premium

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moores Law to bring smart, connected devices to every person on Earth



Other Locations

US, California, Santa Clara



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

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3DIC STCO SOC/Physical Design Engineer

Intel
Hillsboro, OR 97123

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