Barefoot Networks, Inc.
- Computer Engineering
Barefoot Networks, Inc. seeks Hardware Eng. @ 2185 Park Blvd, Palo Alto, CA 94306.
1) Floor Planning of complex/large physical design blocks (up to 4 million instances);
2) Complete placement through timing closure;
3) Complete clock tree synthesis through timing closure;
4) Complete routing through timing closure;
5) Complete static timing analysis through timing closure;
6) Signoff of owned blocks to meet all checklist requirements (set-up, hold, DRC, LVS, etc.);
7) Manual implementation of critical data path blocks (pre-placement, pre-routes, etc.); and
8) Integration of custom blocks and synthesized blocks into complete physical design structures that meet all signoff criteria.
Minimum Requirements: Bachelor’s degree in Electrical Engineering, Electronic Engineering, or Computer Science (or foreign equivalent), plus 5 years (60 months) of experience as a Physical Design Engineer or a related occupation.
This position requires at least 5 years of experience with the following:
1) Static Timing Analysis tool Primetime; and
2) TCL Programming language.
It also requires at least 3 years working with the following:
1) Physical Implementation tool ICC;
2) Physical Verification tool Calibre;
3) Synthesis tool dc-compiler; and
4) Extraction tool star-rc.
To apply, send resume to email@example.com and reference job title.
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